CMOS XNOR gate design | 90 nm technology

In this post, we will discuss the design of a CMOS XNOR gate using Cadence Virtuoso and confirm its functionality using the ADLE tool.

Expected Theoretical Functionality

Q = (A ⊕ B) = A.B + A.B

Inputs [x0,x1]		y
0	0	1
0	1	0
1	0	0
1	1	1

Circuit Diagram with Sizing of the nMOS and pMOS transistors

Test Environment setup

In this setup, we have used the vpulse in order to generate a 16ns pulse with a width of 8ns.

Output Waveforms | Functionality Confirmation

Tpdr = 0.038949ns

Tpdf = 0.02867 ns

Avg PD = 0.0339595ns