In this post, we will discuss how we can design a NAND gate using CMOS 90 nm technology. In order to do this, we are going to use Cadence Virtuoso as our design tool.
Calculations:
1. Fall Delay: 0.01189 ns
2. Rise Delay: 0.00572 ns
Average Dealy : (0.01189ns + 0.00572ns)/2 = 0.008805ns
NAND Gate Truth Table
Inputs (x1, x0)
|
Output(y)
|
|
0
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
0
|
Circuit Diagram With sizing in virtuoso
The reason we have chosen 415nm as the width of PMOS is, the inversion of the output occurs at 415nm when we look at the transfer curve of a CMOS inverter.
Furthermore, this circuit is going to be transformed into a symbol and then that symbol is going to be simulated and then we are going to analyze the delay which is generated from the circuit.
Furthermore, this circuit is going to be transformed into a symbol and then that symbol is going to be simulated and then we are going to analyze the delay which is generated from the circuit.
Simulations from ADEL and confirmation of Functionality
Delay Calculations
Calculations:
1. Fall Delay: 0.01189 ns
2. Rise Delay: 0.00572 ns
Average Dealy : (0.01189ns + 0.00572ns)/2 = 0.008805ns
