CMOS NOT Gate | Layout Design | Cadence Virtuoso

CMOS XNOR gate design | 90 nm technology

In this post, we will discuss the design of a CMOS XNOR gate using Cadence Virtuoso and confirm its functionality using the ADLE tool.

Expected Theoretical Functionality

Q = (A ⊕ B) = A.B + A.B

Inputs [x0,x1]		y
0	0	1
0	1	0
1	0	0
1	1	1

Circuit Diagram with Sizing of the nMOS and pMOS transistors

Test Environment setup

In this setup, we have used the vpulse in order to generate a 16ns pulse with a width of 8ns.

Output Waveforms | Functionality Confirmation

Tpdr = 0.038949ns

Tpdf = 0.02867 ns

Avg PD = 0.0339595ns

CMOS Inverter Desıgn | Testing | Layout Design | DRC and LVS | 90 nm Technology

CMOS Inverter 

In this post, we will discuss how we can design a CMOS inverter using Virtuoso's Layout XL and Schematic view.
For this, I assume that you have a good understanding of the transfer characteristics of CMOS inverter, especially the inversion voltage concept.

Link of Youtube Video where I explain how we can find the width of PMOS for inversion of the input.
https://www.youtube.com/watch?v=tSmhgFOO1wA&t=658s

Expected functionality

Input (x0)	Output (y)
1	0
0	1

CMOS Inverter Schematic

CMOS inverter Test environment (Symbol created assumption)

* Theoretical functionality confirmed.

CMOS Inverter Layout

Note: The body for NMOS is left tap and PMOS is right tap.



DRC Check

LVS Check

Hence we confirmed that the designed layout is matched with the schematic.

CMOS NAND Gate Design | 90 nm Technology

In this post, we will discuss how we can design a NAND gate using CMOS 90 nm technology. In order to do this, we are going to use Cadence Virtuoso as our design tool.

NAND Gate Truth Table

Inputs (x1, x0)		Output(y)
0	0	1
0	1	1
1	0	1
1	1	0

Circuit Diagram With sizing in virtuoso

The reason we have chosen 415nm as the width of PMOS is, the inversion of the output occurs at 415nm when we look at the transfer curve of a CMOS inverter.
Furthermore, this circuit is going to be transformed into a symbol and then that symbol is going to be simulated and then we are going to analyze the delay which is generated from the circuit.

Simulations from ADEL and confirmation of Functionality

Delay Calculations

Calculations:

1. Fall Delay: 0.01189 ns
2. Rise Delay: 0.00572 ns

Average Dealy : (0.01189ns + 0.00572ns)/2 = 0.008805ns